An embodiment of the present invention relates to a voltage generation circuit configured to generate a reference voltage which is not affected by an abnormal power-on reset signal.
In semiconductor memory devices, in particular, in nonvolatile memory devices which can be electrically erased and programmed, to perform an erase operation for erasing data stored in a memory cell and a program operation for storing data in a memory cell, Fowler-Nordheim (FN) tunneling and hot electron injection techniques are being used.
In current memory devices and all fields for developing chips, reducing the size of the devices and chips is becoming a big issue. For this reason, the switch of technology changes quickly and a driving voltage is gradually lowered for a reduced operating power.
A nonvolatile memory device must be supplied with sufficient power for a stable operation, which has led to an increased driver size. On the other hand, to reduce the amount of current for the operation, an external voltage EXT_VDD is not all supplied, but is lowered through a voltage down converter (hereinafter referred to as a ‘VDC’) and then supplied.
To generate the down-converted voltage of VDC or to regularly maintain the voltage level of an operation voltage, a reference voltage Vref for maintaining a constant voltage level is used.
Accordingly, there is a need for a circuit for outputting the reference voltage Vref that is maintained at a constant voltage level.